Memory Technology, Design and Testing: Proceedings, 7th IEEE International Workshop, San Jose, California, 1999

The 14 papers presented at the August 1999 workshop are grouped under the headings of architecture and applications, diagnosis and yield, memory testing topics, and new ideas in technology and design. The topics include unbalanced cache systems, failure mechanisms detected in memory chips during rou...

Ausführliche Beschreibung

Gespeichert in:
1. Verfasser:
Rajsuman, R.
Körperschaften:
IEEE Computer Society, IEEE Computer Society. Technical Committee on VLSI, IEEE Computer Society. Technical Council on Test Technology, IEEE Solid-State Circuits Society
Weitere Verfasser:
Wike, T. R (MitwirkendeR)
Format:
Elektronisch E-Book
Sprache:
Englisch
Veröffentlicht:
[Place of publication not identified] IEEE Computer Society Press 1999
Zusammenfassung:
The 14 papers presented at the August 1999 workshop are grouped under the headings of architecture and applications, diagnosis and yield, memory testing topics, and new ideas in technology and design. The topics include unbalanced cache systems, failure mechanisms detected in memory chips during routine construction analysis, modeling and testing transistor faults in content-addressable memories, a comparative simulation study of four multilevel DRAMs, and low-power SRAM circuit design. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR.
Umfang:
1 online resource
Anmerkungen:
Bibliographic Level Mode of Issuance: Monograph
Anmerkungen:
English
Schlagworte:
Computer storage devices > Congresses.
Bezugswerke: