Formal verification : an essential toolkit for modern VLSI design /
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and present...
Gespeichert in:
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Essential toolkit for modern VLSI design
Essential toolkit for modern very-large scale integration design - Hauptverfasser:
- , ,
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- Format:
- Elektronisch E-Book
- Sprache:
- Englisch
- Veröffentlicht:
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Amsterdam, [Netherlands] :
Morgan Kaufmann,
2015.
- Ausgabe:
- 1st edition
- Zusammenfassung:
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Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific
- Umfang:
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1 online resource (372 p.)
text file - Anmerkungen:
- Description based upon print version of record.
- Anmerkungen:
- English
- Bibliografie:
- Includes bibliographical references at the end of each chapters and index.
- ISBN:
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9780128008157
0128008156
9780128007273
0128007273 - Schlagworte:
- Links: